The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 07, 2002
Filed:
Oct. 15, 1999
Douglas A. Larson, Lakeville, MN (US);
Joseph Jeddeloh, Blaine, MN (US);
Jeffrey J. Rooney, Blaine, MN (US);
Micron Technology, Inc., Boise, ID (US);
Abstract
One embodiment of the present invention provides a method for flexibly allocating I/O pins used for bus grant signals between bus controllers located on a semiconductor chip. The method operates by receiving a first set of grant lines from a first bus arbitration circuit. This first set of grant lines is used to grant control of a first bus to devices on the first bus. The method divides the first set of grant lines into a first subset of grant lines and a second subset of grant lines. The method also receives a second set of grant lines from a second bus arbitration circuit. This second set of grant lines is used to grant control of a second bus to devices on the second bus. The method divides the second set of grant lines into a third subset of grant lines and a fourth subset of grant lines. Next, the method selects outputs from between the first subset of grant lines and the third subset of grant lines, and drives the outputs off of the semiconductor chip through a first set of output pins. During a first mode of operation, the first subset of grant lines is selected to be driven through the first set of output pins, and during a second mode of operation the third subset of grant lines is selected to driven through the first set of output pins.