The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 30, 2002
Filed:
Jun. 01, 2000
Robert C. Aitken, San Jose, CA (US);
Haluk Konuk, Mountain View, CA (US);
Jeff Rearick, Fort Collins, CO (US);
John Stephen Walther, Sunnyvale, CA (US);
Agilent Technologies, Inc, Palo Alto, CA (US);
Abstract
An integrated circuit is provided with Fully Automated Scan Testing (FAST)-lite flip-flop. The integrated circuit has data, scan in, master-hold, clock, scan-into-master, and master to-scan-out inputs. A first transistor circuit is connected to the data, master-hold, and clock inputs and has a first transistor circuit output. A second transistor circuit is connected to the can in and scan-into-master inputs and has a second transistor circuit output. A first flip-flop is connected to the first transistor circuit and second transistor circuit outputs and has a first flip-flop output. A third transistor circuit is connected to the second transistor circuit output and the master-to-scan-out input and has a third transistor circuit output. A second flip-flop latch is connected to the third transistor circuit output has a second flip-flop output. The FAST-lite flip-flop uses the normal functionality of the first flip-flop and second flip-flop to operate either in a normal mode or a test mode for scan testing. The FAST-lite flip-flop is so designated because it uses one less flip-flop than the prior art FAST flip-flop.