The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2002

Filed:

Jul. 05, 2000
Applicant:
Inventor:

Ying Chou Tsai, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/348 ;
U.S. Cl.
CPC ...
H01L 2/348 ;
Abstract

A pattern layout structure of package substrate includes a plurality of patterned circuit layers alternately stacking up with at least an insulative layer for isolating the patterned circuit layers wherein the patterned circuit layers are electrically connected each other. The feature of the pattern layout is that the patterned circuit layer includes a signal circuit region, a power/ground region, and a dummy circuit region. The signal circuit region includes a multiplicity of conductive traces, and the power/ground region includes a first grid-like pattern while the dummy circuit region includes a second grid-like pattern. The pitch of either the first or second grid patterns is equal to the pitch of the conductive traces.


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