Apparatus for issuing instructions and reissuing a previous instructions by recirculating using the delay circuit

Abstract

An instruction decoder that issues new instructions by driving a machine bus ( ) with the correct information during each clock cycle. This information is either extracted from the current instruction to be executed, or is recycled from the previous contents ( ) of the machine bus when a scoreboarding operation has been performed. Mousetrap multiplexer ( ) chooses between several sources of opcode and operand fields and routes them to the machine bus ( ) through several translation stages and multiplexers. The decision of which source to use is based on what kind of instruction is currently being looked at by the instruction queue in the instruction fetch unit. The instruction queue notifies the instruction decoder that the next instruction is to be either a RISC operation (including register, memory, and/or branch instructions) or an instruction which is part of a microcode flow. If a complex macroinstruction flow is in progress, its operands can be accessed through alias registers. This allows indirect access to a source or destination register specified by the operands of the macrocode instruction or the opcode of the macroinstruction while executing a sequence of microinstructions. These aliased operands are maintained by the macroinstruction aliasing logic ( ).