The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 23, 2002
Filed:
Feb. 07, 2000
Tae Wook Seo, Suwon, KR;
Jeon Sig Lim, Kyungki-do, KR;
Samsung Electronics Co., Ltd., Suwon, KR;
Abstract
A method of manufacturing a capacitor having a high storage capacitance and a method of fabricating semiconductor devices incorporating the same include measures to ensure that the substrate and/or components of the device are not thermally damaged during the process of forming a sacrificial structure of doped oxide layers used as a form in producing the storage electrode of the capacitor. The oxide layers are formed over the substrate by LPCVD or PECVD, which processes can be carried out at a temperature of only about 400-600° C. Each one of an adjacent pair of the doped oxide layers has a different etching rate from the other as the result of a difference (type or amount) in impurities contained in the oxide layers. At least one hole is formed in the sacrificial structure to create a side wall of the sacrificial structure. The side wall is etched so that repeating tooth-like prominences and depressions are formed at the side wall as the result of the different etching rates of the oxide layers. Subsequently, a conductive layer, constituting the storage electrode of the capacitor, is formed over the side wall so that the prominences and depressions of the side wall are reproduced in the conductive layer. A silicon HSG layer can be formed on an inner wall surface or on all of the exposed surfaces of the storage electrode to further increase the storage capacitance.