Nitrogenated gate structure for improved transistor performance and method for making same

Abstract

An integrated circuit is provided in which nitrogen is incorporated into the gate dielectric and transistor gate. A method for forming the integrated circuit preferably comprises the providing of a semiconductor substrate that has a p-well and a laterally displaced n-well, each including a channel region laterally displaced between a pair of source/drain regions. Preferably, the semiconductor substrate has a resistivity of approximately 10 to 15 &OHgr;-cm. A dielectric layer is formed on an upper surface of the semiconductor substrate. The formation of the dielectric layer preferably comprises a thermal oxidation performed at a temperature of approximately 600 to 900° C. and the resulting thermal oxide has a thickness less than approximately 50 angstroms. A conductive gate layer is then formed on the dielectric layer. In a preferred embodiment, the conductive gate layer is formed by chemically vapor depositing polysilicon at a pressure of less than approximately 2 torrs at a temperature in the range of approximately 500 to 650° C. A nitrogen bearing impurity distribution is then introduced into the conductive gate layer and the dielectric layer. The introduction of the nitrogen bearing impurity distribution is suitably accomplished by implanting a nitrogen bearing molecule such as N, N , NO, NF , N O, NH , or other nitrogen bearing molecule. Ideally, a peak concentration of the nitrogen bearing impurity distribution is in the range of approximately 1×10 to 1×10 atoms/cm and is located proximal to an interface of the conductive gate layer and the dielectric layer. Thereafter, an anneal may be performed, preferably in a rapid thermal process, at a temperature of approximately 900 to 1100° C. for a duration of less than 5 minutes.