The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 16, 2002
Filed:
Mar. 04, 1999
Ming-Tsung Tung, Hsin-Chu Hsian, TW;
United Microelectronics Corp., Hsin-Chu, TW;
Abstract
A method for forming a laterally diffused metal-oxide semiconductor is disclosed. The invention normally is for forming a transistor device, which includes the following steps. Firstly a semiconductor layer is provided. Then a field insulating region is formed into the semiconductor layer. Sequentially forming a gate dielectric layer over a portion of the field insulating region is carried out. Then forming a deep portion of a first drain/source region within the semiconductor layer and spaced from the field insulating region/the top surface. Here, the deep portion is doped with dopants of a conductivity type, with the deep portion having a first doping concentration. The next step is forming a lightly doped portion of the first drain/source region within the semiconductor layer and a neighbouring portion of the field insulating region/the oxide top surface and adjacent the channel region. Generally the lightly doped portion is doped with dopants of the conductivity type. And there is a second doping concentration which is less than the first doping concentration. A main portion of said first drain/source region within the semiconductor layer is formed. Therefore the main portion neighbors the field insulating region/the oxide top surface and is adjacent the lightly doped portion. Also, the main portion disposed above the deep portion as well as main portion is doped with dopants of the conductivity type and has a third doping concentration, which is less than the first doping concentration and is greater than the second doping concentration. Then a second drain/source region is formed within the semiconductor layer and spaced from the lightly doped portion of the first drain/source region by a channel region, the second drain/source region is doped with dopants of the conductivity type. Finally the process for forming a gate electrode over at least a portion of the channel region and insulated is carried out therefrom.