Semiconductor integrated circuit design and evaluation system using cycle base timing

Abstract

A semiconductor integrated circuit design and evaluation system for designing an LSI device under an electric design automation (EDA) environment and for evaluating a test pattern produced based on the CAD data derived in the design stage of the LSI device. The system includes an EDA environment for designing an LSI device and evaluating functions of the designed LSI device by a device logic simulator, a dump file for storing data expressed by an event base obtained by executing the device logic simulation, an LSI tester simulator for generating a test pattern and an expected value pattern in a cycle base, a cycle-event converter for converting the test pattern from the LSI tester simulator in the cycle base to a test pattern of the event base, a first memory for storing the event based test pattern from the cycle-event converter, a second memory for storing the data from the dump file, and a comparator for synchronizing the data stored in the first and second memories by comparing the timing relationship between the two and extracting output data of the device under test from the dump file corresponding to the test pattern from the LSI tester simulator.