Method and system for high speed detailed placement of cells within an integrated circuit design

Abstract

A method and system for high speed detailed placement of cells within an integrated circuit design. The novel detailed placement system receives a set of cells of an integrated circuit design where the cells have undergone coarse placement. Cells have variable width but the same height (or vice-versa). The cells are each assigned an initial coordinate position, e.g., using floating point precision values. During detailed placement, the cell coordinates are assigned to x-axis and y-axis grid lines. The detailed placement process sorts the cells based on their coordinates along a first axis, e.g., their x-axis coordinates; sort order dictates cell placement order. In one embodiment, sort order preference is given to the wider cells. For a given cell, placement is performed by scanning through the rows of the substrate and selecting the left-most positioned vacant site of each row as a candidate site for placement. A site is vacant if it does not contain a previously placed cell. Of the candidate sites, a valid site having the lowest cost (e.g., the nearest site) is selected for the cell. Some candidate sites are invalid due to the presence of obstructions or incompatible metal layers. A candidate site can also be invalid if it lies too far to the left of the cell, based on a left factor. Placement from left to right along the rows continues in this manner until all cells are placed. Alternatively, the process could run right to left, down to up or up to down.