Method for making an integrated circuit including alignment marks

Abstract

A method for making an integrated circuit preferably includes the steps of: forming a trench laterally adjacent an active region in a semiconductor substrate; forming a dielectric layer on the semiconductor substrate filling the trench and covering the active area; selectively etching the dielectric layer to remove at least a portion of the dielectric layer overlying the active region and to define a recess within the dielectric layer filling the trench to serve as an alignment mark; and polishing the selectively etched dielectric layer and leaving the alignment mark. The method may also include forming an optically opaque layer adjacent the polished dielectric layer and with the alignment mark causing a repeated alignment mark in the optically opaque layer. The alignment mark and/or repeated alignment mark may be used for alignment in a subsequent processing step. The alignment mark can be made with a step height which is greater than a conventional alignment mark formed by the step height difference between the active area and the dielectric layer of the trench. Accordingly, variations in polishing, for example, will not obscure or remove the alignment mark made in accordance with the present invention.