The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 02, 2002
Filed:
May. 22, 1998
Jeffrey R. Brown, Minnetonka, MN (US);
Micron Technology, Inc., Boise, ID (US);
Abstract
A method and computer readable medium are provided for analyzing the integrity of a sensitivity list for a process statement in a hardware description language file. An example of a hardware description language to which the method can be applied is VHDL. The method compares an actual sensitivity list from a hardware description language file to an expected sensitivity list that includes one or more parameters expected to appear in the actual sensitivity list. In the event the actual sensitivity list deviates from the expected sensitivity list, the integrity of the actual sensitivity lists is compromised. In this case, an advisory can be generated to identify the deviation, and note its location within the hardware description language file. In this manner, the designer can quickly find the defective sensitivity list and correct it prior to simulation. A sensitivity list verification method can significantly reduce the time and effort involved in sensitivity list debugging. Consequently, the designer can devote more time and resources to the design effort and the end objective of producing the subject design. In many cases, reduction of debugging costs will bear significantly on the final cost of the design. At the same time, reduction of debugging time can shorten the design cycle.