The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2002

Filed:

Jun. 28, 2000
Applicant:
Inventors:

John Yi, Austin, TX (US);

Terry Marquis, Austin, TX (US);

Assignee:

Advanced Micro Devices, Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B07C 5/344 ;
U.S. Cl.
CPC ...
B07C 5/344 ;
Abstract

Parametric test data is taken on a sampled set of a particular integrated circuit (IC) using both an Automatic Test Equipment (ATE) tester and a system test motherboard. The parametric test data comprises maximum operating frequency, maximum operating temperature and minimum operating power supply voltage. A maximum operating frequency is determined at a particular fixed operating temperature and power supply voltage. A maximum operating temperature is determined at a particular fixed operating frequency and power supply voltage. Finally, a minimum operating power supply voltage is determined at a particular fixed operating frequency and temperature. Multiple two parameter graphs are plotted and the slope or numerical derivative for each plot is calculated as conversion factors. During a normal production run for the particular IC performance limit data is taken on the ATE tester comprising the same three parameters of maximum operating frequency at a particular temperature and power supply voltage. The calculated conversion factors are used to scale the production parametric data from the ATE tester to new calculated expected performance limits. These new performance limits are used to sort production ICs into system performance classes for which the ICs are expected to qualify.


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