Dram cell having a vertical transistor and a capacitor formed on the sidewalls of a trench isolation

Abstract

A DRAM cell capacitor and access transistor are described. Capacitor formation, access transistor fabrication and cell isolation methods are integrated by using isolation trench sidewalls to form DRAM capacitors and access transistors. A doped silicon substrate adjacent to the vertical sidewalls of the isolation trench provides one DRAM cell capacitor plate. The DRAM capacitor also contains a dielectric material that partially covers the interior vertical sidewalls of the isolation trench. A conductive layer covering the dielectric material on the vertical sidewalls of the isolation trench forms the second capacitor plate and completes the DRAM capacitor. A vertically oriented access transistor is formed over top of the capacitor. To accomplish this, an isolation dielectric is deposited and patterned to provide a support structure for gate electrodes of the vertical access transistor above the trench sidewall capacitors. After gate structure formation the support layer is replaced with selectively doped epitaxial silicon in which the transistor's channel, source, and drain are formed.