Built in self test algorithm that efficiently detects address related faults of a multiport memory without detailed placement and routing information

Abstract

In a multiport memory semiconductor integrated circuit, an efficient method of testing the memory for faults. The method determines a base address in a multiport memory. A plurality of addresses are scanned within the memory which are at a hamming distance of 1 from the base address, such that at least two memory cells in each column of the multiport memory device are accessed in the scan. This allows the detection of cross port faults, address mismatch faults, and bit shorts due to the fact that the faults are exposed when the two memory cells sharing access columns are accessed with test data. The method functions nominally without requiring any detailed information about the placement and routing structure of the multiport memory device.