The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 12, 2002
Filed:
Aug. 16, 1999
Youngjin Park, Poughkeepsie, NY (US);
Heon Lee, Fishkill, NY (US);
Infineon Technologies AG, Munich, DE;
Abstract
In accordance with the present invention, a method for forming gate conductors in 4F area stacked capacitor memory cells includes the steps of forming a buried bit line in a substrate, forming an active area above and in contact with the buried bit line and separating portions of the active area by forming a dielectric material in trenches around the portions of the active area. Portions of the dielectric material are removed adjacent to and selective to the portions of the active area. A first portion of a gate conductor is formed in locations from which the portion of dielectric material is removed, and a second portion of the gate conductor is formed on a top surface of the dielectric material and in contact with the first portion of the gate conductor. Stacked capacitors are formed such that the gate conductor activates an access transistor formed in the portions of the active area. A layout is also included.