The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 05, 2002
Filed:
Mar. 15, 1999
Applicant:
Inventors:
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 3/128 ;
U.S. Cl.
CPC ...
G01R 3/128 ;
Abstract
An integrated circuit has a built-in self-test (BIST) arrangement ( ). The built-in self-test arrangement includes a read only memory (ROM), ( ) that stores test algorithm instructions. A ROM logic circuit ( ) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.
Hii, Kuong. (2002). Built-in self-test arrangement for integrated circuit memory devices (U.S. Patent No. 6353563). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6353563
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