The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2002

Filed:

Jan. 18, 2000
Applicant:
Inventors:

David J. Collins, Windham, NH (US);

Craig E. Core, North Andover, MA (US);

Lawrence E. Felton, Hopkinton, MA (US);

Jing Luo, Lexington, MA (US);

Assignee:

Analog Devices, Inc., Norwood, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1302 ;
U.S. Cl.
CPC ...
H01L 2/1302 ;
Abstract

A method for capping active areas of a semiconductor wafer uses photolithography to define areas of sealant on the cap wafer to thereby reduce the amount of space required for attaching the cap wafer to the semiconductor wafer carrying active areas to be capped. Using photolithography in this manner increases the amount of space on the semiconductor wafer that can be used to form active areas which, in turn, improves the density of active area on the semiconductor wafer. In one embodiment, the method includes the steps of applying a photoimageable layer, photoimaging the photoimageable layer to define a pattern including remaining regions of the photoimageable layer and removed regions of the photoimageable layer, and using the pattern to define the sealant regions on the semiconductor wafer. The method may further include one or more steps, such as applying sealant to the sealant regions defined by the pattern, curing the sealant, removing the remaining regions after applying the sealant to the sealant regions, removing excess sealant not within the sealant regions, and using the sealant material to form at least one seal around at least one active area formed on the second semiconductor substrate.


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