The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2002

Filed:

Apr. 12, 1999
Applicant:
Inventors:

Shi-Yu Huang, Tainan, TW;

Ding-Ming Kwai, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 3/128 ;
U.S. Cl.
CPC ...
G01R 3/128 ;
Abstract

A high-speed built-in self-test (BIST) circuit for dynamic random access memory (DRAM) is disclosed. The circuit automatically generates a sequence of pre-defined test patterns for on-chip DRAM testing. The circuit includes two finite state machines, instead of the conventional single finite state machine. Therefore, a pipeline technique can then be applied to divide the pattern generation process into stages, leading to a higher-speed design. In addition to pipelining, protocol-based relaxation is also presented. This technique, imposing a certain protocol on the two communicating finite state machines, further relaxes the timing criticality of the design.


Find Patent Forward Citations

Huang, Shi-Yu. (2002). High speed built-in self-test circuit for drams (U.S. Patent No. 6351837). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6351837

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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