The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 26, 2002
Filed:
Jun. 10, 1999
Takanaga Yamazaki, Tama, JP;
Yasushi Akao, Kokubunji, JP;
Keiichi Kurakazu, Tokorozawa, JP;
Masayasu Ohizumi, Akishima, JP;
Takeshi Kataoka, Tokyo, JP;
Tatsuo Nakai, Kodaira, JP;
Mitsuhiro Miyazaki, Higashimurayama, JP;
Yosuke Murayama, Kodaira, JP;
Other;
Abstract
A data processor including a central processing unit and a plurality of direct map cache memories ( ) has a plurality of area designating circuits ( ) for variably designating location and size of address area in the memory space managed the central processing unit and partially overlaps the address area designated by a plurality of area designating circuits. Thereby, the overlapped area (Eco) has a function as the 2-way set associative cache memory in combination with a plurality of cache memories. For the non-overlapping area, respective cache memory functions as the direct map cache memory. It is previously judged to attain the necessary data processing capability by arranging which processing routine to which address area and then executing such routine with what processing speed. Thereby, when cache object area is assigned to a plurality of cache memory, a plurality of cache memories are combined as a set associative cache for operation to the task which particularly requires high speed operation or to the data. As a result, the system can be optimized by improving the cache hit rate of the necessary area.