Method of manufacturing semiconductor memory device including various contact studs

Abstract

A method of manufacturing a semiconductor device including various contact studs is provided. According to the method, a plurality of contact holes for various metal contact studs aligned to a bit line, a gate, a semiconductor substrate, or an electrode are formed simultaneously after a capacitor formation process. In this case, an etch stop pattern provided for stopping a selective etching process for forming the contact holes covers the bit line or conductive plugs formed on the semiconductor substrate. The thickness of a first etch stop pattern formed on the bit line or an electrode is similar or substantially the same as a second etch stop pattern formed on conductive plugs. To this end, the method involves selectively removing a capping insulating layer on the bit line for a self aligned contact (SAC) process for forming a conductive pad connected to a capacitor and then depositing a separate etch stop layer. Alternatively, the method may involve reducing the thickness of the capping insulating layer to use it as the first etch stop pattern and forming another second etch stop pattern. In this case, a process of patterning an upper electrode of a capacitor is performed, followed by a process of etching the capping insulating layer.