The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 12, 2002
Filed:
Mar. 30, 1999
Low cost silicon substrate with impurity gettering and latch up protection and method of manufacture
Applicant:
Inventors:
Oleg V. Kononchuk, Vancouver, WA (US);
Sergei Koveshnikov, Vancouver, WA (US);
Assignee:
SEH-America, Vancouver, WA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1322 ;
U.S. Cl.
CPC ...
H01L 2/1322 ;
Abstract
A low cost method of manufacturing a silicon substrate having both impurity gettering and protection against CMOS latch up. The method includes performing a low energy implant of a selected acceptor ion to form a low resistivity buried layer closely adjacent the front surface of a silicon wafer. A low energy silicon implant is also performed to create a plurality of gettering sites closely adjacent the front surface. Subsequently, an epitaxial silicon layer is grown on the front surface.