The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 05, 2002
Filed:
Dec. 14, 1999
Jack A. Mandelman, Stormville, NY (US);
Fariborz Assaderaghi, Mahopac, NY (US);
Michael J. Hargrove, Clinton Corners, NY (US);
Peter Smeys, White Plains, NY (US);
Norman J. Rohrer, Underhill, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of forming a silicon on insulator (SOI) body contact at a pair of field effect transistors (FETs), a sense amplifier including a balanced pair of such FETs and a RAM including the sense amplifiers. A pair of gates are formed on a SOI silicon surface layer. A dielectric bridge is formed between a pair of gates when sidewall spacers are formed along the gates. Source/drain (S/D) conduction regions are formed in the SOI surface layer adjacent the sidewalls at the pair of gates. The dielectric bridge blocks selectively formation of S/D conduction regions. A passivating layer is formed over the pair of gates and the dielectric bridge. Contacts are opened partially through the passivation layer. Then, a body contact is opened through the bridge to SOI surface layer and a body contact diffusion is formed. Contact openings are completed through the passivation layer at the S/D diffusions. Tungsten studs are formed in the contact openings.