The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 05, 2002

Filed:

Jul. 24, 2000
Applicant:
Inventors:

Chih-Jen Huang, Hsin-Chu, TW;

Chia-Te Wu, Tai-Hsi Hsiang, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/1336 ;
Abstract

A method for fabricating a non-volatile memory on the semiconductor substrate is disclosed. First of all, a plurality of trench isolation regions are formed. Then, firstly implanting ions of a first conductivity type and second conductivity type are carried out. Secondly implanting ions of the first conductivity type and second conductivity type are carried out. Then, a first oxide layer is deposited and the first oxide layer is removed. A second oxide layer is deposited. A portion of second oxide is removed, thus, a portion of second oxide layer is remained. A third oxide layer is formed. A first polysilicon layer is formed. The first polysilicon layer is etched. A oxide-nitride-oxide layer is formed. Consequentially, the oxide-nitride-oxide layer are all etched. The second polysilicon on is formed. A portion of the second polysilicon layer, a portion of the first polysilicon layer, a portion of the third oxide layer and a portion of the second oxide layer are all etched. Thus, capacitor columns are formed.


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