Method of forming insulating spacers in dram chips

Abstract

There is disclosed an improved method of forming the spacer which isolates the gate conductor from the metal contact with the diffusion (source/drain) region of each array transfer transistor for all memory cells of a DRAM chip. According to the method there is provided a structure consisting of a silicon substrate having a diffusion region formed therein and gate conductor (GC) lines formed thereon. Then, an oxynitride layer and a silicon nitride (Si N ) layer are conformally deposited in sequence onto the structure by LPCVD in the same tool for total clusterization. Next, the structure is anisotropically dry etched with a chemistry that is Si N /oxynitride selective to expose the oxynitride layer between the GC lines and the upper portion thereof in a one step process to form the Si N spacers. Still in accordance with the invention, the above method finds a valuable application in the fabrication of borderless metal contacts in DRAM chips wherein the risk of having potential an electrical short between the gate conductor and the metal contact is substantially eliminated.