The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 22, 2002

Filed:

Sep. 03, 1998
Applicant:
Inventors:

Hiroshi Mizuno, Tsukuba, JP;

Osamu Kinoshita, Ushiku, JP;

Tetsuaki Murohashi, Ushiku, JP;

Akihisa Ueno, Tsukuba, JP;

Yoshifumi Sakuma, Tsukuba, JP;

Kostas Amberiadis, San Jose, CA (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/1302 ; H01L 2/1461 ; B24B 1/00 ;
U.S. Cl.
CPC ...
H01L 2/1302 ; H01L 2/1461 ; B24B 1/00 ;
Abstract

A method for chemical-mechanical polishing of a layer that is deposited on a surface of an integrated circuit substrate is described. The method includes: (1) immobilizing the integrated circuit substrate using a substrate holder such that the integrated circuit substrate surface is positioned against a surface of a polishing pad, which is mounted on a supporting surface; (2) a first stage of polishing the substrate surface including maintaining a predetermined difference between the rotational velocity of the polishing pad and the rotational velocity of the substrate holder allowing an endpoint of the chemical-mechanical polishing process of the layer to be detected; and (3) a second stage of polishing the substrate such that the rotational velocity of the polishing pad and the rotational velocity of the substrate holder are substantially the same to produce a substantially planar substrate surface.


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