The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 15, 2002

Filed:

Jun. 23, 2000
Applicant:
Inventors:

Johann Alsmeier, Radebeul, DE;

Carl John Radens, LaGrangeville, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/7108 ;
U.S. Cl.
CPC ...
H01L 2/7108 ;
Abstract

A layout pattern for increasing the spacing between the deep trenches of one cell pair and the deep trenches of an adjacent cell pair in an array of semiconductor DRAM cell pairs each of which cell pairs share a common bitline contact to bitlines arranged in one direction and each of which cell pairs are coupled to gate conductors arranged orthogonal to the bitlines. The layout pattern is formed by positioning the deep trenches of all of said pairs along alternate bitlines so they are offset from said bitlines along gate conductors in opposing directions. The deep trenches of all of the remaining bitlines are offset from said bitlines in opposing directions opposite to the opposing directions of said trenches along said alternate bitlines so as to form a herringbone pattern of cells.


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Alsmeier, Johann. (2002). Dram cell layout for node capacitance enhancement (U.S. Patent No. 6339239). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6339239

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