The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2002

Filed:

Dec. 30, 1998
Applicant:
Inventors:

Masashi Kitazawa, Tokyo, JP;

Masayoshi Shirahata, Tokyo, JP;

Tomohiro Yamashita, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/900 ;
U.S. Cl.
CPC ...
H01L 2/900 ;
Abstract

A narrow trench ( ) is formed in a memory circuit region ( ) and a wide trench ( ) is formed in a logic circuit region ( ). An oxide ( B) is formed by CVD to fill the trench ( ) and planarization is performed thereon. A thin oxide film ( ) is formed by thermal oxidation in an active region, and a polysilicon ( A) for gate electrode is formed and etched only in the memory circuit region ( ). At this time, the polysilicon ( B) remains in a seam ( ). An oxide film ( ) is deposited by CVD, to play the first role of covering the seam ( ) and the second role of constituting a thick oxide film together with the oxide film ( ). Thus, the trenches of different widths and the oxide films of different thicknesses are formed in a semiconductor substrate, to solve the problem of burying failure which is likely to occur in a narrow trench.


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