The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 01, 2002
Filed:
May. 09, 2000
Jeremy Lansford, Austin, TX (US);
Advanced Micro Devices, Inc., Austin, TX (US);
Abstract
A method includes providing a first wafer having at least one process layer formed thereon. A portion of a first process layer is removed using a polishing process. A portion of at least one of the first process layer and a second process layer is removed using a buffing process for a pre-selected duration of time. A buffed surface of at least one of the first process layer and the second process layer is inspected to determine a post-buff defect density for the inspected process layer. The duration of the buffing process is adjusted for a second wafer based on the determined post-buff defect density of the inspected process layer. A system includes a processing tool, at least one metrology tool, and a process controller. The processing tool is adapted to remove at least a portion of a first process layer of a first wafer using a buffing process for a pre-selected duration of time. The at least one metrology tool is adapted to determine a post-buff defect density of at least one of the first process layer and a second process layer. The process controller is coupled to at least one of the processing tool and the at least one metrology tool. The process controller is adapted to receive the determined post-buff defect density from the at least one metrology tool, and adjust the duration of the buffing process for a second wafer based on the determined post-buff defect density of the first wafer.