Error correcting circuit for making efficient error correction, and involatile semiconductor memory device incorporating the same error correcting circuit

Abstract

This invention provides a nonvolatile semiconductor memory device capable of avoiding complicatedness of algorithm for normal write operation and a write operation prior to erasing in a memory system in which the distribution of threshold of cells after erasing is adjusted. This nonvolatile semiconductor memory device generates check bits as error correction code according to a check bit generating matrix so formed that in both the normal write operation and the write operation prior to erasing, the factors of “1” of respective rows satisfy the quantity absolutely necessary for generating check bits and the quantity of the factors of “1” is an odd number.