The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 11, 2001
Filed:
Jul. 31, 2000
Jeffrey D. Currin, Pleasanton, CA (US);
Jacob Herbold, Portland, OR (US);
Manohari Reddy, Beaverton, OR (US);
Mark Dahl, Beaverton, OR (US);
Philip T. Kuglin, Tualatin, OR (US);
Credence Systems Corporation, Fremont, CA (US);
Abstract
A random access memory (RAM) having N addressable storage locations is addressed by input data specifying a signal delay, and the RAM reads out control data controlling the delay of a delay circuit. A linearization system automatically adjusts the value of the control data stored at each of the RAM's N addresses so that the delay provided by the delay circuit is a linear function of the value of the input data. The linearization system provides two periodic reference signals (“beat” and “clock”) wherein the period P,of the beat signal and the period P,of the clock signal are related by the expression P,=P,(N+1)/N. The linearization system iteratively adjusts the control data stored at each RAM address so that when the RAM continuously reads out the control data stored at the Kth RAM address, the Kth edge of the beat signal and every Nth edge thereafter substantially coincides with an edge of the delay circuit output signal.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile