The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 11, 2001
Filed:
Oct. 13, 1999
Mark J. Mercer, Tuscon, AZ (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A method and apparatus for trimming the level and slope in a voltage reference using current-switching DACs to inject small correction currents into or draw currents from the voltage reference circuit. Each DAC is controlled via a programmable non-volatile memory, which can be programmed after final packaging. Thus, the present technique enables trimming the voltage reference circuit after the circuit has been packaged. For the slope trim, the current is injected into or drawn from one side or the other of the band-gap core cell. The level trim DAC sources a correction current into or sinks a correction current from the resistor chain that sets the voltage level at the base of the transistors in the band-gap core. The level and slope trim DACs generate currents that are precise multiples of the currents through the resistors being trimmed. Thus the corrections are invariant with process and temperature, the necessary trim range is minimized, and the shape of the remaining error (curvature) is not altered. This current replication technique has the same effect as an ideal trim, i.e. produces the same result as changing the values of the resistors around which the trim circuits are placed.