Inter-module buffer determination methodology for asic synthesis

Abstract

One embodiment of the present invention provides a method for designing a circuit that limits the impact of design changes within a module of a circuit to the characteristics of signals flowing between modules of the circuit. This method operates by dividing the circuit into a plurality of circuit modules, and defining a plurality of interface modules located between the plurality of circuit modules. These interface modules include drivers coupled between upstream circuit module outputs and downstream circuit module inputs, so as to isolate the downstream circuit module inputs from the upstream circuit module outputs. Next, the circuit modules and interface modules are designed, and a synthesized circuit is ultimately generated from the designs. This synthesized circuit is then verified for characteristics such as timing. If it fails to verify, design changes are made. In one embodiment, these design changes include: re-specifying constraints for modules, re-generating designs for modules, and re-dividing the circuit into modules. By locating drivers within separate interface modules, the drive strengths of the drivers can be more easily specified. Furthermore, by locating the drivers at particular positions within an interface module, the signals flowing through the drivers can be guided to flow in such a way as to route signals along shorter, more optimal pathways between modules.