The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 04, 2001
Filed:
Dec. 28, 1999
Mahadevamurty Nemani, Sunnyvale, CA (US);
Franklin Baez, San Jose, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A method, system and computer program product for automatically determining optimal design parameters of a subsystem to meet design constraints. The subsystem comprises a plurality of circuits. The optimal design parameters are determined by performing a parameter-delay curve optimization of the subsystem design parameters. Specifically, an embodiment of the present invention provides a method and/or computer program product for determining optimal values for the design parameters of a circuit block, which result in optimally assigned delay targets for datapath blocks at the minimum power/area point. The problem/solution space is extended to solve the problem of figuring out the best possible implementation, for example, static vs dynamic, for each datapath block. Based on parameter functions, which relate to the design parameters for circuits in the circuit block, the design parameters are optimized to satisfy the design constraints. In one embodiment, the design parameters include power and delay and the parameter functions are power-delay curves.