The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 04, 2001
Filed:
Feb. 23, 2000
Applicant:
Inventors:
Hiroyuki Shinogi, Gunma, JP;
Nobuyuki Takai, Gunma, JP;
Ryoji Tokushige, Gunma, JP;
Yukihiro Takao, Gunma, JP;
Katsuhiko Kitagawa, Gunma, JP;
Assignee:
Sanyo Electric Co., Ltd., Osaka, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/176 ;
U.S. Cl.
CPC ...
H01L 2/176 ;
Abstract
A removal area EL is provided as a first dicing line in a dicing area, coat materials,′ and,′ are put on the flanks of the removal area, a resin layer R is formed, and a dicing blade narrower than the width of the removal area EL is used to fully cut on a second dicing line, whereby the interface exposed by the first dicing can be coated and protected.
Shinogi, Hiroyuki. (2001). Chip size package and manufacturing method thereof (U.S. Patent No. 6326701). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6326701
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile