Method of fabricating a flash memory cell

Abstract

A semiconductor wafer is provided having a substrate, and a tunneling oxide layer is formed thereon. A sacrificial layer defining an active region is formed over the tunneling oxide layer, and a defined first polysilicon layer is formed on the tunneling oxide layer within the active region and covered by the sacrificial layer. The process sequence includes: performing an etching process using the sacrificial layer as a mask to form a STI pattern, forming a dielectric layer that fills the STI pattern, performing a planarization process to remove the dielectric layer over the sacrificial layer, performing a first etch back process to remove a pre-selected thickness of the dielectric layer over the STI pattern, forming a second polysilicon layer, performing a second etch back process to form a spacer connecting with the first polysilicon layer, removing the sacrificial layer, forming an insulating layer on the surface of the spacer and the first polysilicon layer, forming a control gate on the insulating layer, and performing an ion implantation process to form a source and a drain on the substrate within the active region.