The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 27, 2001
Filed:
Sep. 14, 1998
Applicant:
Inventor:
Larry L. Moresco, San Carlos, CA (US);
Assignee:
Fujitsu Limited, , JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G05B 1/302 ; G06F 1/900 ; H03M 1/300 ;
U.S. Cl.
CPC ...
G05B 1/302 ; G06F 1/900 ; H03M 1/300 ;
Abstract
A method of determining the most cost effective manner in which to provide a given number of memory or logic gates for a particular application. The method takes into consideration both the cost per memory bit of fabricating memory cells on a semiconductor chip as a function of the number of memory cells on the chip (i.e, the chip size), and the costs of assembling multiple memory chips into a larger memory device using different assembly and packaging configurations. By considering the fabrication and packaging costs together, the most economically efficient combination of memory chip size and packaging method to produce a desired memory capacity can be determined.