High-speed, compact, edge-triggered, flip-flop circuit

Abstract

A high-speed, compact, edge-triggered flip-flop circuit is provided which includes an input circuit section, a latch circuit section and an output circuit section. The input circuit section includes at least one transistor such as a field-effect transistor (FET) which determines the logic function of the flip-flop such as D, S-R, or T, and provides a first stage of latching. The input circuit section receives the logic control signals such as D, S-R, or T, and a clock signal. In one embodiment of the invention, the latch circuit section includes two series-connected negative differential resistance (NDR) diodes. In this embodiment, a common terminal of the two NDR diodes is connected to the data output of the input circuit section and to the data input of the output circuit section. In the first embodiment, the output circuit section includes a plurality of FETs which perform second stage of latching such that the output of this section reflects the logic of the chosen inputs only at the occurrence of either a low-to-high transition or a high-to-low transition on the clock signal, but not both, depending on the chosen configuration of the flip-flop circuit. In a second embodiment, a D flip-flop circuit includes a latch circuit section which includes at least one NDR diode connected to the data output of the input circuit section and an output circuit section which also includes at least one NDR diode connected to the output of the output circuit section. In the second embodiment, the flip-flop circuit may use: 1) bistable NDR logic; 2) cascaded NDR latches; or 3) pseudo-bistable NDR logic with a true, single-phase clock.