Semiconductor memory device having an array of memory cells including a select transistor and a storage capacitor wiring lines at 45° angles

Abstract

A semiconductor memory device is provided, which prevents the characteristic of storage capacitors from degrading without chip-area increase of memory cells. Each of storage capacitors has a dielectric sandwiched by lower and upper electrodes. The lower electrodes are formed by a patterned, common electrically-conductive layer. The dielectrics are formed by a patterned, common ferroelectric layer formed on the common electrically-conductive layer which is entirely overlapped with the common electrically-conductive layer. The upper electrodes are regularly arranged on the common ferroelectric layer and are located outside the rows and columns of a matrix array where the windows of the common electrically-conductive layer and common ferroelectric layer are aligned. Wiring lines are formed over the upper electrodes through an interlayer insulating layer covering the storage capacitors, thereby electrically connecting the upper electrodes and select transistors.