Electrical overlay/spacing monitor method using a ladder resistor

Abstract

A method and structure is disclosed to measure spacing and misalignment of features in semiconductor integrated circuits. Three equally spaced, parallel first level conductive lines are formed on a first insulating layer with staircase patterns projecting both out of and into the inner edges of the outer lines. A second insulating layer is deposited and step contact vias are opened through the second insulating layer over the steps of the staircase patterns. The inner edge of the step contact via coincides with the inner edge of the step. Contact pad vias are opened through the second insulating layer over the outer lines and the step contact vias and the contact pad vias are filled with conductive material. A second level conductive line is formed over the second insulating layer parallel to said first level conductive lines and above the central first level conductive line. Resistor ladder patterns are formed projecting from both edges of said second level conductive line, the rungs of said ladder patterns being of equal length and being composed of rung conductive sections with a resistor section interposed. A center conductor contact pad is formed electrically connected to the second level conductive line. A right conductor contact pad is formed over the right contact pad via and a left conductor contact pad is formed over the left contact pad via. The resistances between the center conductor pad and the right conductor pad and between the center conductor pad and left conductor pad are measured. From these resistances are inferred which rungs of the resistor ladder patterns make contact with step contact vias of the outer first level conductive lines. This infers bounds for the distances, SR and SL, from the right and left outer first level conductive lines to the second level conductive line. Spacing and misalignment are calculated from these distances.