Method for manufacturing low stress metallic interconnect lines for use in integrated circuits

Abstract

A process for manufacturing metallic interconnect lines of low stress. Process steps according to the present invention first include a step of providing a semiconductor substrate (e.g. a silicon wafer) with an overlying insulating layer, followed by forming a multi-layer stack on the insulating layer. The multi-layer stack includes at least two adjoining layers: one being a metal M layer (for example an aluminum layer) and the other being a material Q layer, where material Q is a material that forms either (i) an electrically conductive intermetallic layer, or (ii) an electrically conducting solid solution layer, with metal M when subjected to the subsequent thermal treatment step. Silicon and titanium meet this requirement when metal M is aluminum. The multi-layer stack is then pattered to form a multi-layer metallic interconnect line. An interconnect dielectric material layer (e.g. a SiO,or silicon nitride layer) is subsequently formed at a temperature T,, covering the multi-layer metallic interconnect line. The multi-layer metallic interconnect line and the interconnect dielectric material layer are then thermally treated at a temperature T,that is greater than T,, in order to reduce the stress (i.e. compressive or tensile) of the multi-layer metallic interconnect line by forming the electrically conductive intermetallic layer or electrically conductive solid solution layer. The result is a low stress metallic interconnect line.