Delayed start oscillator circuit

Abstract

A delayed start oscillator includes an oscillator enable signal having first and second states thereof for selectively enabling and disabling the oscillator respectively. An oscillator output signal has first and second levels thereof responsive to the first state of the oscillator enable signal for providing an oscillator output signal. A timing circuit is coupled to a supply voltage line for providing a timing signal output indicative of a selected delayed start duration and a plurality of series connected inverting stages are coupled to receive the oscillator output signal and the timing signal. The oscillator output signal remains at a first level for the delayed start duration in response to the timing signal and subsequently transitions between the first and second levels at an operational frequency determined by the plurality of inverting stages until the oscillator enable signal transitions to the second state thereof. The delayed start oscillator is operational to provide an output clock signal at a constant rate following a selectively delayed startup time and can be used, for example, in dynamic memory cell-based integrated circuit devices incorporating a-self-refresh mode or other special modes of operation wherein an initial start-up delay in entering the particular mode is desired and in which the initial delay is longer than the clock period of the signal then controlling the mode.