The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 13, 2001

Filed:

Dec. 14, 1998
Applicant:
Inventors:

John J. Seliskar, Colorado Springs, CO (US);

David W. Daniel, Divide, CO (US);

Todd A. Randazzo, Colorado Springs, CO (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/7082 ;
U.S. Cl.
CPC ...
H01L 2/7082 ;
Abstract

High energy implantation through varying vertical thicknesses of one or more films is used to form a vertically modulated sub-collector, which simultaneously reduces both the vertical and lateral components of parasitic collector resistance in a vertically integrated bipolar device. The need for a sinker implant or other additional steps to reduce collector resistance is avoided. The necessary processing modifications may be readily integrated into conventional bipolar or BiCMOS process flows.


Find Patent Forward Citations

Seliskar, John. (2001). Mev implantation to form vertically modulated n+ buried layer in an npn bipolar transistor (U.S. Patent No. 6316817). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6316817

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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