The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 06, 2001
Filed:
Mar. 31, 2000
Jen-Tai Hsu, El Dorado Hills, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An input/output (I/O) buffer having an output node tolerant of an externally applied high voltage signal is powered by a lower voltage supply potential and comprises a n-well region and a bias generation circuit that generates a reference voltage at an internal node. A PMOS pull-up transistor is coupled between the lower voltage supply potential and the output node, and NMOS pull-down transistor is coupled between the output node and a ground reference potential. First and second PMOS charging transistors each of their gates coupled to the internal node, with the first PMOS charging transistor being coupled between the output node and the gate of the PMOS pull-up transistor. The second PMOS charging transistor is coupled between the output node and the n-well region. The first and second charging transistors operate to pass a pad voltage applied to the output node to the gate of the PMOS pull-up transistor and the n-well region, respectively, when the pad voltage reaches or exceeds the lower voltage supply potential.