The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 06, 2001
Filed:
Mar. 21, 2000
John Jianshi Wang, San Jose, CA (US);
Hao Fang, Cupertino, CA (US);
Masaaki Higashitani, Sunnyvale, CA (US);
Other;
Abstract
A method (,) of forming a NAND type flash memory device includes the steps of forming an oxide layer (,) over a substrate (,) and forming a first conductive layer (,) over the oxide layer. The first conductive layer (,) is etched to form a gate structure (,) in a select gate transistor region (,) and a floating gate structure (,) in a memory cell region (,). A first insulating layer (,) is then formed over the memory cell region (,) and a second conductive layer (,) is formed over the first insulating layer (,). A word line (,) is patterned in the memory cell region (,) to form a control gate region and source and drain regions (,) are formed in the in the substrate (,) in a region adjacent the word line (,) and in a region adjacent the gate structure (,). A second insulating layer (,) is formed over both the select gate transistor region (,) and the memory cell region (,) and first and second contact openings are formed in the second insulating layer (,) down to the gate structure (,) and the control gate region, wherein a depth (X) through the second insulating layer (,) down to the gate structure (,) and down to the control gate region are approximately the same, thereby eliminating a substantial overetch of the gate structure contact opening.