The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 30, 2001
Filed:
Dec. 29, 1998
Bradford B. Congdon, Olympia, WA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A user-friendly, PCI bus-compliant plug-in management card is provided to evaluate a PCI bus in a host computer system for correct operation. The PCI management card is provided with a PCI bus controller ASIC for tracking error and fault conditions which may occur on a PCI bus and reporting such error and fault conditions locally or remotely over a computer network. The PCI bus controller ASIC may be implemented with a reset snoop which snoops the PCI bus for a bus reset; a clock snoop which snoops the PCI bus for a bus clock changing frequency or dying; a cycle timer which begins counting when a bus cycle starts, resets the counting when the bus cycle ends, and triggers an alarm indicating a hung cycle when the bus cycle has not ended after a predetermined time period; a cycle snoop which snoops the bus for any illegal handshake and any hung cycle triggered from the cycle timer; and an error capture which captures all error and failure conditions snooped from the reset snoop, the clock snoop, the cycle timer, and reports such error and failure conditions to a local processor for transmission to a host system, or to a remote system over a computer network for remote system management.