The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 30, 2001

Filed:

Oct. 29, 1998
Applicant:
Inventors:

Ken Inoue, Tokyo, JP;

Hitoshi Abiko, Tokyo, JP;

Minoru Higuchi, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
C23C 1/434 ; H01L 2/144 ;
U.S. Cl.
CPC ...
C23C 1/434 ; H01L 2/144 ;
Abstract

There is provided a method for manufacturing a semiconductor device for forming a silicide layer of metal of high melting point, wherein the metal of high melting point is processed in sputtering under a condition in which no deterioration is produced by the sputtering apparatus. There is also provided a sputtering apparatus for manufacturing semiconductor device. In the method of the present invention, a high melting point metal is accumulated on a silicon substrate formed with a gate electrode of a semiconductor element to form a metallic film of high melting point, thereafter it is heat treated to form a silicide layer of the high melting point metal at an interface layer with the metallic film with high melting point, and in this case, the metallic film of high melting point is accumulated in sputtering by a magnetron sputtering device under a condition in which an electrical load amount Q reaching to the gate electrode is less than 5 C/cm,. In addition, the sputtering apparatus,has the collimator plate,including an electrical conductive material having many through-pass holes passed from the target toward the wafer between the target holder,and the wafer holder,while it is being connected to an earth terminal.


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