The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 23, 2001
Filed:
Sep. 21, 2000
Nobuaki Otsuka, Tokyo, JP;
Yasushi Kameda, Kanagawa-ken, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
A semiconductor device has an output buffer having transistors connected in parallel for an external driving purpose, a connection terminal connected to an external resistor, and an output impedance controller connected to the connection terminal and the output buffer, for adjusting the impedance of the output buffer in accordance with the external resistor. The output impedance controller has a first transistor of a first conductivity type having a drain connected to the connection terminal; a first level-controller connected to a gate of the first transistor, for controlling the level of the gate of the first transistor to set the connection terminal to a predetermined voltage level; a second transistor having a gate connected to the gate of the first transistor and a source connected to a source of the first transistor; a first dummy transistor group consisting of transistors that are of a second conductivity type, are connected to the second transistor, correspond to the output buffer transistors, and are connected in parallel; a first controller connected to the second transistor and the first dummy transistor group, for controlling the first dummy transistor group to equalize the level of a connection node between the second transistor and the first dummy transistor group with the predetermined voltage level; and a second controller for controlling the output buffer transistors according to the control carried out by the first controller.