Semiconductor device having metal silicide regions of differing thicknesses above the gate electrode and the source/drain regions, and method of making same

Abstract

The present invention is directed to a semiconductor device (,) having enhanced electrical performance characteristics, and a method of making such a device. In one illustrative embodiment, the semiconductor device (,) is comprised of a polysilicon gate electrode (,) positioned above a gate insulation layer (,), a plurality of source/drain regions (,) formed in a semiconducting substrate (,), a first metal silicide region (,A) positioned above the gate electrode (,), a second metal silicide region (,) positioned above each of the source/drain regions (,), wherein the first metal silicide region (,A) is approximately 2-10 times thicker than each of the second metal silicide regions (,). In one illustrative embodiment, the inventive method disclosed herein comprises forming a first layer of a refractory metal (,) above a layer of polysilicon (,), and converting the refractory metal layer (,) to a metal suicide layer (,), and patterning the metal silicide layer (,) and the gate electrode layer (,) to form a metal silicide region (,A) above the gate electrode (,). The method further comprises forming a plurality of source/drain regions (,) in the substrate (,), forming a second layer comprised of a refractory metal above at least the gate stack (,) and the source/drain regions (,). The method concludes with converting at least a portion of the second layer of refractory metal to a second metal silicide region above each of the source/drain regions (,).