Generating candidate architectures for an architectural exploration based electronic design creation process

Abstract

Candidate architectures for an electronic design are created through a machine implemented method that includes initially generating one or more initial candidate architectures for the electronic design on a top abstraction level, and subsequently generating additional candidate architectures for the electronic design at one or more lower abstraction level, in accordance with periodic guidance provided by a designer. In one embodiment, the initial candidate architectures on the top abstraction level are generated in accordance with a behavioral specification of the electronic design, and an initial set of constraints on the electronic design, independently described, and include application of a de-abstraction transformation. Candidate architectures on the lower abstraction levels are generated by performing de-abstraction transformations on generated candidate architectures of immediately higher abstraction levels, taking into consideration changes made by the designer to constraints of the electronic design, if any. Additional candidate architectures on the top abstraction level may also be generated in like manner with a current modified set of constraints instead. In one embodiment, the de-abstraction transformations include resource allocation, resource scheduling, finite state machine extractions, resource binding and resource sharing. In one embodiments, candidate architectures, regardless of abstraction levels, are generated in real time.