The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 16, 2001
Filed:
May. 21, 1998
Applicant:
Inventors:
Howard Y. M. Tang, San Jose, CA (US);
Albert Chan, Palo Alto, CA (US);
Cyrus Y. Tsui, Los Altos, CA (US);
Ju Shen, Milpitas, CA (US);
Assignee:
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 7/38 ; H03K 1/9173 ; G01R 3/128 ;
U.S. Cl.
CPC ...
G06F 7/38 ; H03K 1/9173 ; G01R 3/128 ;
Abstract
An input/output circuit in an In-system programmable (ISP) logic device allows an output signal from a boundary scan register to be provided as output during programming operations of said ISP logic device. Thus, the ISP logic circuit can provide valid data output to other circuits interfaced to the ISP logic circuit during programming of the ISP logic device, thereby obviating a need to reset the system after reprogramming of the ISP logic device.